1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. Particularly, the present invention relates to a method of manufacturing a salicide layer and more particularly, to a method of manufacturing a salicide layer on a gate structure.
2. Description of the Related Art
Usually, silicide is formed On the gates, the source/drain region or the interconnects to lower the contact resistance between the semiconductor devices on a substrate. Since lattice of the silicide is rearranged when it is treated by high-temperature annealing, the defects in the silicide are eliminated, wherein the defects are eliminated, and perfect grains are grown instead of defective grains. A crystalline structure is formed in the silicide after a high-temperature annealing is performed so that the resistance of the silicide is lowered. Hence, the contact resistance can be reduced by forming a silicide layer on the gates, the source/drain region or the interconnects. Currently, the process of self-aligned silicide (salicide) is widely used in the integrated circuits industry.
FIGS. 1A through 1B are schematic, cross-sectional views of the conventional process for manufacturing a salicide layer on a semiconductor substrate.
As shown in FIG. 1A, a substrate 100 having agate structure 102 is provided. A light implantation step is used to form a lightly doped source/drain region 110 adjacent to the gate structure 102 in the substrate 100. A spacer 104 is formed on the sidewall of the gate structure 102. The gate structure 102 comprises a gate oxide layer 106 and a gate electrode 108.
As shown in FIG. 1B, a heavy implantation step is used to form a source/drain region 112 in the substrate 100 exposed by the gate structure 102 and the spacer 104. A titanium layer (not shown) is formed over the substrate 100. A thermal process is performed to convert portions of the titanium layer above the gate electrode 108 and the source/drain region 112 into a silicide layer 114, which is a titanium nitride layer. The remaining titanium layer, which is not converted into the silicide layer, is stripped away to finish the process of manufacturing a salicide layer.
Since portions of silicon in or on the gate electrode 108 and the source/drain region 112 diffuse to the spacer 104 to spread onto the surface of the spacer 104 as temperature is rises, a silicide layer 116 is formed on the spacer 104, when the silicide layer 114 is formed on the gate electrode 108 and the source/drain region 112. In such a circumstance, when the silicide layer 116 connects the gate electrode 108 and the source/drain region 112, it results in a bridging effect. Hence, an undesired electrical coupling occurs between semiconductor devices, and the yield is low.
In order to prevent bridging effects from occurring between the devices, the thermal process is performed at a relatively low temperature of about 700-750.degree. C. to reduce the diffusion of the silicon from the gate electrode 108 and the source/drain region 112 into the spacer 104, especially from the surface portion of the gate electrode, which results in the lateral formation of salicide. However, the relatively low temperature of the thermal process produces a salicide with a relatively poor quality, so the goal of reducing the contact resistance cannot be achieved.
Therefore, there is a need to provide a method for reducing salicide lateral growth, which maintains the desired performance between semiconductor devices and avoids the bridging effect therebetween.